38 research outputs found

    Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance

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    High-Level Synthesis (HLS) is the process of developing digital circuits from behavioral specifications. It involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the controller synthesis. Evolutionary Algorithms have been already effectively applied to HLS to find good solution in presence of conflicting design objectives. In this paper, we present an evolutionary approach to HLS that extends previous works in three respects: (i) we exploit the NSGA-II, a multi-objective genetic algorithm, to fully automate the design space exploration without the need of any human intervention, (ii) we replace the expensive evaluation process of candidate solutions with a quite accurate regression model, and (iii) we reduce the number of evaluations with a fitness inheritance scheme. We tested our approach on several benchmark problems. Our results suggest that all the enhancements introduced improve the overall performance of the evolutionary search

    Timing Analysis in High-Level Synthesis

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    ... for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore di#erent scheduling possibilities as well as di#erent optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach

    A fast pseudo-Boolean constraint solver

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    High-Level State Machine Specification and Synthesis

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    Current synthesis methodologies based on hardware-description languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however, the initial specification lies between a pure behavioral description and a completely structural one. This paper presents a method and algorithms for exploring the design space between the register-transfer and behavioral levels. The method consists of the specification of a high-level state machine, which combines the advantages of a specific control structure, by means of states and transitions, with the flexibility of behavioral descriptions inside each high-level state. High-level synthesis techniques are used for synthesizing this machine. As a result, the user has control over the final controller implementation and is able to perform high-level trade-o#s between control and data-path

    Verity- A formal

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    Impaired Neovascularization in Aging

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    Recent Advances: Several studies have found significant differences during wound healing between younger and older individuals. The hypoxia-inducible factor 1-alpha (HIF-1 alpha) signaling pathway has recently been identified as a major player in wound healing. Hypoxia-inducible factors (HIFs) are pleiotropic key regulators of oxygen homeostasis. HIF-1 alpha is essential to neovascularization through its regulation of cytokines, such as SDF-1 alpha (stromal cell-derived factor 1-alpha) and has been shown to upregulate the expression of genes important for a hypoxic response. Prolyl hydroxylase domain proteins (PHDs) and factor inhibiting HIF effectively block HIF-1 alpha signaling in normoxia through hydroxylation, preventing the signaling cascade from activating, leading to impaired tissue survival. Critical Issues: Aged wounds are a major clinical burden, resisting modern treatment and costing millions in health care each year. At the molecular level, aging has been shown to interfere with PHD regulation, which in turn prevents HIF-1 alpha from activating gene expression, ultimately leading to impaired healing. Other studies have identified loss of function in cells during aging, impeding processes such as angiogenesis. Future Directions: An improved understanding of the regulation of molecular mediators, such as HIF-1 alpha and PHD, will allow for manipulation of the various factors underlying delayed wound healing in the aged. The findings highlighted in this may facilitate the development of potential therapeutic approaches involved in the alteration of cellular dynamics and aging

    Design Of Provably Correct Storage Arrays

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    In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register transfer level (RTL) specification with a low-level transistor implementation. Equivalence checking is increasingly applied in practical design flows to verify regular logic components. However, because of their specific organization and circuit techniques, high-performance implementations of large storage arrays require particular modifications to the general flow that make them suitable for formal equivalence checking. Two techniques are outlined in this paper. First, a special hierarchical verification scheme is described that allows the application of a partitioned comparison approach of the bit-wise organized transistor-level model with the word-wise organized RTL model. Second, a modified switch-level extraction technique is presented that extends the applicability of equivalence checking from regular dynamic CMOS circuits to self-resetting CMOS (SRCMOS) circuits

    Justification-Based Local Search with Adaptive Noise Strategies

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    Abstract. We study a framework called BC SLS for a novel type of stochastic local search (SLS) for propositional satisfiability (SAT). Aimed specifically at solving real-world SAT instances, the approach works directly on a non-clausal structural representation for SAT. This allows for don’t care detection and justification guided search heuristics in SLS by applying the circuit-level SAT technique of justification frontiers. In this paper we extend the BC SLS approach first by developing generalizations of BC SLS which are probabilistically approximately complete (PAC). Second, we develop and study adaptive noise mechanisms for BC SLS, including mechanisms based on dynamically adapting the waiting period for noise increases. Experiments show that a preliminary implementation of the novel adaptive, PAC generalization of the method outperforms a well-known CNF level SLS method with adaptive noise (AdaptNovelty+) on a collection of structured real-world SAT instances.
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